System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-194
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[17] - Reserved, RES0.
[16] nTWI Not trap WFI.
0
If a WFI instruction executed at EL0 would cause execution to be suspended, such as if there
is not a pending WFI wakeup event, it is taken as an exception to EL1 using the 0x1 ESR code.
1
WFI instructions are executed as normal.
[15:14] - Reserved,
RES0.
[13] V Vectors bit. This bit selects the base address of the exception vectors:
0
Normal exception vectors, base address
0x00000000
. Software can remap this base address
using the VBAR.
1
High exception vectors, base address
0xFFFF0000
. This base address is never remapped.
The input VINITHI defines the reset value of the V bit.
[12] I Instruction cache enable bit. This is a global enable bit for instruction caches:
0
Instruction caches disabled. If SCTLR.M is set to 0, instruction accesses from stage 1 of the
EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner Non-cacheable,
Outer Non-cacheable.
1
Instruction caches enabled. If SCTLR.M is set to 0, instruction accesses from stage 1 of the
EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner Write-Through,
Outer Write-Through.
Table 4-193 SCTLR bit assignments (continued)
Bits Name Function
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