ARM Cortex-A53 MPCore - Page 109

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-48
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MRS <Xt>, CTR_EL0 ; Read CTR_EL0 into Xt
Register access is encoded as follows:
4.3.27 Data Cache Zero ID Register
The DCZID_EL0 characteristics are:
Purpose Indicates the block size written with byte values of zero by the
DC ZVA
(Cache Zero by Address), system instruction.
Usage constraints This register is accessible as follows:
Configurations There are no configuration notes.
Attributes DCZID_EL0 is a 32-bit register.
Figure 4-25 shows the DCZID_EL0 bit assignments.
Figure 4-25 DCZID_EL0 bit assignments
Table 4-61 shows the DCZID_EL0 bit assignments.
To access the DCZID_EL0:
MRS <Xt>, DCZID_EL0 ; Read DCZID_EL0 into Xt
Table 4-60 CTR_EL0 access encoding
op0 op1 CRn CRm op2
11 011 0000 0000 001
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
RO RO RO RO RO RO
4
RES
0
35
BlockSize
DZP
063
Table 4-61 DCZID_EL0 bit assignments
Bits Name Function
[63:5] - Reserved,
RES0.
[4] DZP Prohibit the
DC ZVA instruction:
0 DC ZVA instruction permitted.
1 DC ZVA instruction is prohibited.
[3:0] BlockSize Log2 of the block size in words:
0b0100 The block size is 16 words.