Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-10
ID021414 Non-Confidential
Table A-7 Retention power management signals
Signal Direction Description
CPUQACTIVE[CN:0] Output Indicates whether the referenced processor is active
CPUQREQn[CN:0] Input Indicates that the power controller is ready to enter or exit retention for the referenced
processor
CPUQDENY[CN:0] Output Indicates that the referenced processor denies the power controller retention request
CPUQACCEPTn[CN:0] Output Indicates that the referenced processor accepts the power controller retention request
NEONQACTIVE[CN:0] Output Indicates whether the referenced Advanced SIMD and Floating-point block is active
NEONQREQn[CN:0] Input Indicates that the power controller is ready to enter or exit retention for the referenced
Advanced SIMD and Floating-point block
NEONQDENY[CN:0] Output Indicates that the referenced Advanced SIMD and Floating-point block denies the power
controller retention request
NEONQACCEPTn[CN:0] Output Indicates that the referenced Advanced SIMD and Floating-point block accepts the
power controller retention request
L2QACTIVE Output Indicates whether the L2 data RAMs are active
L2QREQn Input Indicates that the power controller is ready to enter or exit retention for the L2 data
RAMs
L2QDENY Output Indicates that the L2 data RAMs deny the power controller retention request
L2QACCEPTn Output Indicates that the L2 data RAMs accept the power controller retention request
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