ARM Cortex-A53 MPCore - Page 195

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-134
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• If two or more memory error events from different RAMs, that do not match the RAMID,
bank, way, or index information in this register while the sticky Valid bit is set, occur in
the same cycle, the Other error count field is incremented only by one.
To access the L2MERRSR_EL1:
MRS <Xt>, S3_1_C15_C2_3 ; Read L2MERRSR_EL1 into Xt
MSR S3_1_C15_C2_3, <Xt> ; Write Xt into L2MERRSR_EL1
4.3.82 Configuration Base Address Register, EL1
The CBAR_EL1 characteristics are:
Purpose Holds the physical base address of the memory-mapped GIC CPU
interface registers.
Usage constraints This register is accessible as follows:
Configurations There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes CBAR_EL1 is a 64-bit register.
Figure 4-75 shows the CBAR_EL1 bit assignments.
Figure 4-75 CBAR_EL1 bit assignments
Table 4-120 shows the CBAR_EL1 bit assignments.
To access the CBAR_EL1:
MRS <Xt>, S3_1_C15_C3_0 ; Read CBAR_EL1 into Xt
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
63 18 17
0
RES0
40 39
PERIPHBASE[39:18]
RES0
Table 4-120 CBAR_EL1 bit assignments
Bits Name Function
[63:40] - Reserved,
RES0.
[39:18] PERIPHBASE[39:18] The input PERIPHBASE[39:18] determines the reset value.
[17:0] - Reserved,
RES0.