Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-28
ID021414 Non-Confidential
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-9 shows the PMPIDR0 bit assignments.
Figure 12-9 PMPIDR0 bit assignments
Table 12-18 shows the PMPIDR0 bit assignments.
The PMPIDR0 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE0
.
Peripheral Identification Register 1
The PMPIDR1 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMPIDR1 can be accessed through the internal memory-mapped
interface and the external debug interface.
The accessibility to the PMPIDR1 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMPIDR1 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-10 shows the PMPIDR1 bit assignments.
Figure 12-10 PMPIDR1 bit assignments
Table 12-18 PMPIDR0 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] Part_0
0xD3
Least significant byte of the performance monitor part number.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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