Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-29
ID021414 Non-Confidential
Table 12-19 shows the PMPIDR1 bit assignments.
The PMPIDR1 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE4
.
Peripheral Identification Register 2
The PMPIDR2 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The accessibility to the PMPIDR2 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
The PMPIDR2 can be accessed through the internal memory-mapped
interface and the external debug interface.
Configurations The PMPIDR2 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-11 shows the PMPIDR2 bit assignments.
Figure 12-11 PMPIDR2 bit assignments
Table 12-20 shows the PMPIDR2 bit assignments.
Table 12-19 PMPIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] DES_0
0xB
ARM Limited. This is the least significant nibble of JEP106 ID code.
[3:0] Part_1
0x9
Most significant nibble of the performance monitor part number.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-20 PMPIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Revision
0x2
r0p2.
[3] JEDEC
0b1
RAO. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011
ARM Limited. This is the most significant nibble of JEP106 ID code.
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