Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-30
ID021414 Non-Confidential
The PMPIDR2 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE8
.
Peripheral Identification Register 3
The PMPIDR3 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMPIDR3 can be accessed through the internal memory-mapped
interface and the external debug interface.
The accessibility to the PMPIDR3 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMPIDR3 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-12 shows the PMPIDR3 bit assignments.
Figure 12-12 PMPIDR3 bit assignments
Table 12-21 shows the PMPIDR3 bit assignments.
The PMPIDR3 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFEC
.
Peripheral Identification Register 4
The PMPIDR4 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMPIDR4 can be accessed through the internal memory-mapped
interface and the external debug interface.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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