Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-31
ID021414 Non-Confidential
The accessibility to the PMPIDR4 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMPIDR4 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-13 shows the PMPIDR4 bit assignments.
Figure 12-13 PMPIDR4 bit assignments
Table 12-22 shows the PMPIDR4 bit assignments.
The PMPIDR4 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFD0
.
Peripheral Identification Register 5-7
No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They
are reserved for future use and are
RES0.
12.8.3 Component Identification Registers
There are four read-only Component Identification Registers, Component ID0 through
Component ID3. Table 12-23 shows these registers.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-22 PMPIDR4 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Size
0x0
Size of the component. Log2 the number of 4KB pages from the start of the component to the end
of the component ID registers.
[3:0] DES_2
0x4
ARM Limited. This is the least significant nibble JEP106 continuation code.
Table 12-23 Summary of the Component Identification Registers
Register Value Offset
Component ID0
0x0D 0xFF0
Component ID1
0x90 0xFF4
Component ID2
0x05 0xFF8
Component ID3
0xB1 0xFFC
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