Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-32
ID021414 Non-Confidential
The Component Identification Registers identify Performance Monitor as ARM PMUv3
architecture. The Component ID registers are:
• Component Identification Register 0.
• Component Identification Register 1.
• Component Identification Register 2 on page 12-33.
• Component Identification Register 3 on page 12-34.
Component Identification Register 0
The PMCIDR0 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMCIDR0 can be accessed through the internal memory-mapped
interface and the external debug interface.
The accessibility to the PMCIDR0 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMCIDR0 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-14 shows the PMCIDR0 bit assignments.
Figure 12-14 PMCIDR0 bit assignments
Table 12-24 shows the PMCIDR0 bit assignments.
The PMCIDR0 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF0
.
Component Identification Register 1
The PMCIDR1 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMCIDR1 can be accessed through the internal memory-mapped
interface and the external debug interface.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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