Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-33
ID021414 Non-Confidential
The accessibility to the PMCIDR1 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMCIDR1 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-15 shows the PMCIDR1 bit assignments.
Figure 12-15 PMCIDR1 bit assignments
Table 12-25 shows the PMCIDR1 bit assignments.
The PMCIDR1 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF4
.
Component Identification Register 2
The PMCIDR2 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMCIDR2 can be accessed through the internal memory-mapped
interface and the external debug interface.
The accessibility to the PMCIDR2 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMCIDR2 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-16 on page 12-34 shows the PMCIDR2 bit assignments.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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