ARM Cortex-A53 MPCore - Page 488

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-34
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Figure 12-16 PMCIDR2 bit assignments
Table 12-26 shows the PMCIDR2 bit assignments.
The PMCIDR2 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF8 .
Component Identification Register 3
The PMCIDR3 characteristics are:
Purpose Provides information to identify a Performance Monitor component.
Usage constraints The PMCIDR3 can be accessed through the internal memory-mapped
interface and the external debug interface.
The accessibility to the PMCIDR3 by condition code is:
Table 12-1 on page 12-4 describes the condition codes.
Configurations The PMCIDR3 is in the Debug power domain.
Attributes See the register summary in Table 12-15 on page 12-23.
Figure 12-17 shows the PMCIDR3 bit assignments.
Figure 12-17 PMCIDR3 bit assignments
Table 12-27 shows the PMCIDR3 bit assignments.
RES0
31 0
PRMBL_2
78
Table 12-26 PMCIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_2
0x05 Preamble byte 2.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
RES0
31 0
PRMBL_3
78
Table 12-27 PMCIDR3 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_3
0xB1 Preamble byte 3.