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ARM Cortex-A53 MPCore - Page 606

ARM Cortex-A53 MPCore
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Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-18
ID021414 Non-Confidential
A.11.2 Write address channel signals
Table A-19 shows the write address channel signals for the ACE interface.
A.11.3 Write data channel signals
Table A-20 shows the write data channel signals for the ACE interface.
Table A-19 Write address channel signals
Signal Direction Description
AWADDRM[43:0] Output Write address.
AWBARM[1:0] Output Write barrier type.
AWBURSTM[1:0] Output Write burst type.
AWCACHEM[3:0] Output Write cache type.
AWDOMAINM[1:0] Output Write shareability domain type.
AWIDM[4:0] Output Write address ID.
AWLENM[7:0] Output Write burst length.
AW LO CK M Output Write lock type.
AW PRO TM[ 2: 0 ] Output Write protection type.
AWREADYM Input Write address ready.
AWSIZEM[2:0] Output Write burst size.
AWSNOOPM[2:0] Output Write snoop request type.
AWUNIQUEM Output For WriteBack, WriteClean and WriteEvict transactions.
Indicates that the write is:
0
Shared.
1
Unique.
AW VA LIDM Output Write address valid.
Table A-20 Write data channel signals
Signal Direction Description
WDATAM[127:0] Output Write data
WIDM[4:0] Output Write data ID
WLASTM Output Write data last transfer indication
WREADYM Input Write data ready
WSTRBM[15:0] Output Write byte-lane strobes
WVALIDM Output Write data valid

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