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ARM Cortex-A53 MPCore - Page 607

ARM Cortex-A53 MPCore
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Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-19
ID021414 Non-Confidential
A.11.4 Write data response channel signals
Table A-21 shows the write data response channel signals for the ACE master interface.
A.11.5 Read address channel signals
Table A-22 shows the read address channel signals for the ACE master interface.
Table A-21 Write data response channel signals
Signal Direction Description
BIDM[4:0] Input Write response ID
BREADYM Output Write response ready
BRESPM[1:0] Input Write response
BVALIDM Input Write response valid
Table A-22 Read address channel signals
Signal Direction Description
ARADDRM[43:0] Output Read address.
The top 4 bits communicate only the ACE virtual address for DVM messages.
The top 4 bits are Read-as-Zero if a DVM message is not being broadcast.
ARBARM[1:0] Output Read barrier type.
ARBURSTM[1:0] Output Read burst type.
ARCACHEM[3:0] Output Read cache type.
ARDOMAINM[1:0] Output Read shareability domain type.
ARIDM[5:0] Output Read address ID.
ARLENM[7:0] Output Read burst length.
ARLOCKM Output Read lock type.
ARPROTM[2:0] Output Read protection type.
ARREADYM Input Read address ready.
ARSIZEM[2:0] Output Read burst size.
ARSNOOPM[3:0] Output Read snoop request type.
ARVALIDM Output Read address valid.

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