System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-91
ID021414 Non-Confidential
MRS <Xt>, TCR_EL2 ; Read EL2 Translation Control Register
MSR TCR_EL2, <Xt> ; Write EL2 Translation Control Register
4.3.50 Virtualization Translation Control Register, EL2
The VTCR_EL2 characteristics are:
Purpose Controls the translation table walks required for the stage 2 translation of
memory accesses from Non-secure EL0 and EL1, and holds cacheability
and shareability information for the accesses.
Usage constraints This register is accessible as follows:
Any of the bits in VTCR_EL2 are permitted to be cached in a TLB.
Configurations VTCR_EL2 is architecturally mapped to AArch32 register VTCR.See
Virtualization Translation Control Register on page 4-233.
Attributes VTCR_EL2 is a 32-bit register.
Figure 4-46 shows the VTCR_EL2 bit assignments.
Figure 4-46 VTCR_EL2 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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