ARM Cortex-A53 MPCore - Page 151

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-90
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Table 4-84 shows the TCR_EL2 bit assignments.
To access the TCR_EL2:
Table 4-84 TCR_EL2 bit assignments
Bits Name Function
[63:32] - Reserved,
RES0.
[31] - Reserved,
RES1.
[30:24] - Reserved,
RES0.
[23] - Reserved,
RES1.
[22:21] - Reserved,
RES0.
[20] TBI Top Byte Ignored. Indicates whether the top byte of the input address is used for address match.
The possible values are:
0 Top byte used in the address calculation.
1 Top byte ignored in the address calculation.
[19] - Reserved,
RES0.
[18:16] PS Physical address size. The possible values are:
0b000 32 bits, 4 GB.
0b001 36 bits, 64 GB.
0b010 40 bits, 1 TB.
Other values are reserved.
[15:14] TG0 TTBR0_EL2 granule size. The possible values are:
0b00 4 KB.
0b10 64 KB.
[13:12] SH0 Shareability attribute for memory associated with translation table walks using TTBR0_EL2.
The possible values are:
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer shareable.
0b11 Inner shareable.
[11:10] ORGN0 Outer cacheability attribute for memory associated with translation table walks using
TTBR0_EL2. The possible values are:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0 Inner cacheability attribute for memory associated with translation table walks using
TTBR0_EL2. The possible values are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] - Reserved,
RES0.
[5:0] T0SZ
Size offset of the memory region addressed by TTBR0_EL2. The region size is 2
(64-T0SZ)
bytes.