System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-89
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4.3.49 Translation Control Register, EL2
The TCR_EL2 characteristics are:
Purpose Controls translation table walks required for stage 1 translation of a
memory access from EL2 and holds cacheability and shareability
information.
TCR_EL2 is part of:
• The Virtual memory control registers functional group.
• The Hypervisor and virtualization registers functional group.
Usage constraints This register is accessible as follows:
Configurations TCR_EL2 is architecturally mapped to AArch32 register HCTR. See Hyp
Translation Control Register on page 4-232.
Attributes TCR_EL2 is a 32-bit register.
Figure 4-45 shows the TCR_EL2 bit assignments.
Figure 4-45 TCR_EL2 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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