System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-88
ID021414 Non-Confidential
To access the TCR_EL1:
MRS <Xt>, TCR_EL1 ; Read TCR_EL1 into Xt
MSR TCR_EL1, <Xt> ; Write Xt to TCR_EL1
[25:24] IRGN1 Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. The possible
values are:
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Cacheable.
0b11
Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[23] EPD1 Translation table walk disable for translations using TTBR1_EL1. Controls whether a translation table walk is
performed on a TLB miss for an address that is translated using TTBR1_EL1. The possible values are:
0
Perform translation table walk using TTBR1_EL1.
1
A TLB miss on an address translated from TTBR1_EL1 generates a Translation fault. No
translation table walk is performed.
[22] A1 Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The possible values are:
0
TTBR0_EL1.ASID defines the ASID.
1
TTBR1_EL1.ASID defines the ASID.
[21:16] T1SZ
Size offset of the memory region addressed by TTBR1_EL1. The region size is 2
(64-T1SZ)
bytes.
[15:14] TG0 TTBR0_EL1 granule size. The possible values are:
0b00
4 KB.
0b10
64 KB.
[13:12] SH0 Shareability attribute for memory associated with translation table walks using TTBR0_EL1. The possible
values are:
0b00
Non-shareable.
0b01
Reserved.
0b10
Outer shareable.
0b11
Inner shareable.
[11:10] ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. The possible
values are:
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Cacheable.
0b11
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0 Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. The possible
values are:
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Cacheable.
0b11
Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] - Reserved,
RES0.
[5:0] T0SZ
Size offset of the memory region addressed by TTBR0_EL1. The region size is 2
(64-T0SZ)
bytes.
Table 4-83 TCR_EL1 bit assignments (continued)
Bits Name Function
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