System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-87
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Table 4-83 shows the TCR_EL1 bit assignments.
Table 4-83 TCR_EL1 bit assignments
Bits Name Function
[63:39] - Reserved,
RES0.
[38] TBI1 Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the
TTBR1_EL1 region. The possible values are:
0
Top byte used in the address calculation.
1
Top byte ignored in the address calculation.
[37] TBI0 Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the
TTBR0_EL1 region. The possible values are:
0
Top byte used in the address calculation.
1
Top byte ignored in the address calculation.
[36] AS ASID size. The possible values are:
0
8-bit.
1
16-bit.
[35] - Reserved,
RES0.
[34:32] IPS Intermediate Physical Address Size. The possible values are:
0b000
32 bits, 4 GB.
0b001
36 bits, 64 GB.
0b010
40 bits, 1 TB.
All other values are reserved.
[31:30] TG1 TTBR1_EL1 granule size. The possible values are:
0b00
4 KB.
0b10
64 KB.
[29:28] SH1 Shareability attribute for memory associated with translation table walks using TTBR1_EL1. The possible
values are:
0b00
Non-shareable.
0b01
Reserved.
0b10
Outer shareable.
0b11
Inner shareable.
[27:26] ORGN1 Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. The possible
values are:
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Cacheable.
0b11
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
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