System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-86
ID021414 Non-Confidential
4.3.48 Translation Control Register, EL1
The TCR_EL1 characteristics are:
Purpose Determines which Translation Base Registers defines the base address
register for a translation table walk required for stage 1 translation of a
memory access from EL0 or EL1 and holds cacheability and shareability
information.
TCR_EL1 is part of the Virtual memory control registers functional group.
Usage constraints This register is accessible as follows:
Configurations TCR_EL1 is architecturally mapped to AArch32 register TTBCR(NS).
See Hyp Translation Control Register on page 4-232.
Attributes TCR_EL1 is a 64-bit register.
Figure 4-44 shows the TCR_EL1 bit assignments.
Figure 4-44 TCR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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