ARM Cortex-A53 MPCore - Page 154

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-93
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations DACR32_EL2 is architecturally mapped to AArch32 register DACR
(NS). See Domain Access Control Register on page 4-235.
Attributes DACR32_EL2 is a 32-bit register.
Figure 4-47 shows the DACR32_EL2 bit assignments.
Figure 4-47 DACR32_EL2 bit assignments
Table 4-86 shows the DACR32_EL2 bit assignments.
To access the DACR32_EL2:
MRS <Xt>, DACR32_EL2 ; Read DACR32_EL2 into Xt
MSR DACR32_EL2, <Xt> ; Write Xt to DACR32_EL2
4.3.52 Translation Table Base Register 0, EL3
The TTBR0_EL3 characteristics are:
Purpose Holds the base address of the translation table for the stage 1 translation of
memory accesses from EL3.
Usage constraints This register is accessible as follows:
Configurations TTBR0_EL3 is mapped to AArch32 register TTBR0 (S). See Translation
Table Base Register 0 on page 4-224.
Attributes TTBR0_EL3 is a 64-bit register.
Figure 4-48 on page 4-94 shows the TTBR0_EL3 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 4-86 DACR32_EL2 bit assignments
Bits Name Function
[31:0] D<n>, bits
[2n+1:2n], for
n = 0 to 15
Domain n access permission, where n = 0 to 15. Permitted values are:
0b00 No access. Any access to the domain generates a Domain fault.
0b01 Client. Accesses are checked against the permission bits in the translation tables.
0b11 Manager. Accesses are not checked against the permission bits in the translation tables.
The value
0b10 is reserved.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW