System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-94
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Figure 4-48 TTBR0_EL3 bit assignments
Table 4-87 shows the TTBR0_EL3 bit assignments.
To access the TTBR0_EL3:
MRS <Xt>, TTBR0_EL3 ; Read TTBR0_EL3 into Xt
MSR TTBR0_EL3, <Xt> ; Write Xt to TTBR0_EL3
4.3.53 Translation Control Register, EL3
The TCR_EL3 characteristics are:
Purpose Controls translation table walks required for stage 1 translation of memory
accesses from EL3 and holds cacheability and shareability information for
the accesses.
TCR_EL3 is part of the Virtual memory control registers functional group.
Usage constraints This register is accessible as follows:
Configurations TCR_EL3 is mapped to AArch32 register TTBR(S).
Attributes TCR_EL3 is a 32-bit register.
Figure 4-49 on page 4-95 shows the TCR_EL3 bit assignments.
Table 4-87 TTBR0_EL3 bit assignments
Bits Name Function
[63:48] - Reserved,
RES0.
[47:0] BADDR[47:x] Translation table base address, bits[47:x]. Bits [x-1:0] are
RES0.
x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule
size.
For instructions on how to calculate it, see the ARM
®
Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile.
The value of x determines the required alignment of the translation table, that must be aligned to 2
x
bytes.
If bits [x-1:0] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:0] are treated as if all the bits are zero. The value read
back from those bits is the value written.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
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