ARM Cortex-A53 MPCore - Page 369

Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-4
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Table 7-2 shows the key features in each of the supported ACE configurations.
Table 7-3 shows the permitted combinations of these signals and the supported configurations
in the Cortex-A53 processor, with a CHI bus.
Table 7-4 shows the key features in each of the supported CHI configurations.
Table 7-2 Supported features in the ACE configurations
Features
Configuration
AXI3 mode
ACE
non-coherent,
no L3 cache
ACE
non-coherent,
with L3 cache
ACE outer
coherent
ACE inner
coherent
AXI3 compliance Yes No No No No
ACE compliance No Yes Yes Yes Yes
Barriers on AR and AW channels No
Yes
a
Yes
a
Yes
a
Yes
a
Cache maintenance requests on AR channel No No Yes Yes Yes
Snoops on AC channel No No No Yes Yes
Coherent requests on AR or AW channel No No No Yes Yes
DVM requests on AR channel No No No No Yes
a. Only true if SYSBARDISABLE is LOW. If SYSBARDISABLE is HIGH then barriers are not broadcast.
Table 7-3 Supported CHI configurations
Signal
Feature
CHI non-coherent CHI outer coherent CHI inner coherent
No L3
cache
With L3
cache
No L3
cache
With L3
cache
No L3
cache
With L3
cache
BROADCASTCACHEMAINT 010101
BROADCASTOUTER 001111
BROADCASTINNER 000011
Table 7-4 Supported features in the CHI configurations
Features
Configuration
CHI
non-coherent,
no L3 cache
CHI
non-coherent,
with L3 cache
CHI
outer coherent
CHI
inner coherent
Cache maintenance requests on TXREQ channel No Yes Yes Yes
Snoops on RXREQ channel No No Yes Yes
Coherent requests on TXREQ channel No No Yes Yes
DVM requests on TXREQ channel No No No Yes