Level 2 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 7-5
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7.2.2 Snoop and maintenance requests
The SCU controls snoop and maintenance requests to the system using the external
BROADCASTINNER, BROADCASTOUTER, and BROADCASTCACHEMAINT pins:
• When you set the BROADCASTINNER pin to 1 the inner shareability domain extends
beyond the Cortex-A53 processor and Inner Shareable snoop and maintenance operations
are broadcast externally. When you set the BROADCASTINNER pin to 0 the inner
shareability domain does not extend beyond the Cortex-A53 processor.
• When you set the BROADCASTOUTER pin to 1 the outer shareability domain extends
beyond the Cortex-A53 processor and outer shareable snoop and maintenance operations
are broadcast externally. When you set the BROADCASTOUTER pin to 0 the outer
shareability domain does not extend beyond the Cortex-A53 processor.
• When you set the BROADCASTCACHEMAINT pin to 1 this indicates to the
Cortex-A53 processor that there are external downstream caches and maintenance
operations are broadcast externally. When you set the BROADCASTCACHEMAINT
pin to 0 there are no downstream caches external to the Cortex-A53 processor.
• If you set the BROADCASTINNER pin to 1 you must also set the
BROADCASTOUTER pin to 1.
• In a system that contains Cortex-A53 processors and other processors in a big.LITTLE
configuration, you must ensure the BROADCASTINNER and BROADCASTOUTER
pins on both processors are set to HIGH so that both processors are in the same Inner
Shareable domain.
• Cacheable loads and stores to a shareability domain, that does not extend beyond the
Cortex-A53 processor, can allocate data to the L1 and L2 caches. However they do not
make coherent requests on the master for these accesses. Instead, they use only
ReadNoSnoop or WriteNoSnoop transactions. This always includes non-shareable
memory, and might include inner shareable and outer shareable memory, depending on
the setting of the BROADCASTINNER and BROADCASTOUTER pins.
• If the system sends a snoop to the Cortex-A53 processor for an address that is present in
the L1 or L2 cache, but the line in the cache is in a shareability domain that does not
extend beyond the cluster, then the snoop is treated as missing in the cluster.
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