ARM Cortex-A53 MPCore - Page 425

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-23
ID021414 Non-Confidential
0x830 DBGWVR3_EL1[31:0] RW 64 Debug Watchpoint Value Register 0,
0x834 DBGWVR3_EL1[63:32]
0x838 DBGWCR3_EL1 RW 32 Debug Watchpoint Control Registers, EL1 on page 11-11
0x83C-0xCFC - - - Reserved
0xD00 MIDR RO 32 Main ID Register, EL1 on page 4-14
0xD04-0xD1C - - - Reserved
0xD20 ID_AA64PFR0_EL1[31:0] RO 64 AArch64 Processor Feature Register 0 on page 4-37
0xD24 ID_AA64PFR0_EL1[63:32]
0xD28 ID_AA64DFR0_EL1[31:0] RO 64 AArch64 Debug Feature Register 0, EL1 on page 4-39
0xD2C ID_AA64DFR0_EL1[63:32]
0xD30 ID_AA64ISAR0_EL1[31:0] RO 64 AArch64 Instruction Set Attribute Register 0, EL1 on page 4-40
0xD34 ID_AA64ISAR0_EL1[63:32]
0xD38 ID_AA64MMFR0_EL1[31:0] RO 64 AArch64 Memory Model Feature Register 0, EL1 on page 4-41
0xD3C ID_AA64MMFR0_EL1[63:32]
0xD40 ID_AA64PFR1_EL1[31:0] RO 64 Processor Feature Register 1, RES0
0xD44 ID_AA64PFR1_EL1[63:32]
0xD48 ID_AA64DFR1_EL1[31:0] RO 64 Debug Feature Register 1, RES0
0xD4C ID_AA64DFR1_EL1[63:32]
0xD50 ID_AA64ISAR1_EL1[31:0] RO 64 Instruction Set Attribute Register 1 low word, RES0
0xD54 ID_AA64ISAR1_EL1[63:32]
0xD58 ID_AA64MMFR1_EL1[31:0] RO 64 Memory Model Feature Register 1 low word, RES0
0xD5C ID_AA64MMFR1_EL1[63:32]
0xD60-0xEFC - - - Reserved
0xF00 EDITCTRL RW 32 External Debug Integration Mode Control Register on
page 11-25
0xF04-0xF9C - - - Reserved
0xFA0 DBGCLAIMSET_EL1 RW 32 Debug Claim Tag Set register on page 11-13
0xFA4 DBGCLAIMCLR_EL1 RW 32 Debug Claim Tag Clear Register
0xFA8 EDDEVAFF0 RO 32 Multiprocessor Affinity Register on page 4-15
0xFAC EDDEVAFF1 RO 32 External Debug Device Affinity Register 1, RES0
0xFB0 EDLAR WO 32 External Debug Lock Access Register
0xFB4 EDLSR RO 32 External Debug Lock Status Register
0xFB8 DBGAUTHSTATUS_EL1 RO 32 Debug Authentication Status Register
Table 11-11 Memory-mapped debug register summary (continued)
Offset Name Type Width Description