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ARM Cortex-A53 MPCore - Page 428

ARM Cortex-A53 MPCore
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Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-26
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDDEVID is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-9 shows the EDDEVID bit assignments.
Figure 11-9 EDDEVID bit assignments
Table 11-13 shows the EDDEVID bit assignments.
The EDDEVID can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFC8
.
11.8.3 External Debug Device ID Register 1
The EDDEVID1 characteristics are:
Purpose Provides extra information for external debuggers about features of the
debug implementation.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDDEVID1 is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-10 on page 11-27 shows the EDDEVID1 bit assignments.
Off DLK OSLK EDAD SLK Default
-- - - - RO
31 0
RES0
34
PC Sample
28 27 24 23
RES0 AuxRegs
Table 11-13 EDDEVID bit assignments
Bits Name Function
[31:28] - Reserved,
RES0.
[27:24] AuxRegs Indicates support for Auxiliary registers:
0x0
None supported.
[23:4] - Reserved,
RES0.
[3:0] PC Sample Indicates the level of sample-based profiling support using external debug registers 40 to 43:
0x3
EDPCSR, EDCIDSR and EDVIDSR are implemented.
Off DLK OSLK EDAD SLK Default
-- - - - RO

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