ARM Cortex-A53 MPCore - Page 429

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-27
ID021414 Non-Confidential
Figure 11-10 EDDEVID1 bit assignments
Table 11-14 shows the EDDEVID1 bit assignments.
The EDDEVID1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFC4 .
11.8.4 Peripheral Identification Registers
The Peripheral Identification Registers provide standard information required for all
components that conform to the ARM Debug Interface v5 specification. They are a set of eight
registers, listed in register number order in Table 11-15.
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the
eight Peripheral ID Registers define a single 64-bit Peripheral ID.
The Debug Peripheral ID registers are:
• Peripheral Identification Register 0 on page 11-28.
• Peripheral Identification Register 1 on page 11-28.
• Peripheral Identification Register 2 on page 11-29.
• Peripheral Identification Register 3 on page 11-30.
• Peripheral Identification Register 4 on page 11-31.
• Peripheral Identification Register 5-7 on page 11-31.
31 0
RES0
34
PCSROffset
Table 11-14 EDDEVID1 bit assignments
Bits Name Function
[31:4] - Reserved,
RES0.
[3:0] PCSROffset Indicates the offset applied to PC samples returned by reads of EDPCSR:
0x2 EDPCSR samples have no offset applied and do not sample the instruction set state in
AArch32 state.
Table 11-15 Summary of the Peripheral Identification Registers
Register Value Offset
Peripheral ID4
0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0x03 0xFE0
Peripheral ID1 0xBD 0xFE4
Peripheral ID2 0x2B 0xFE8
Peripheral ID3 0x00 0xFEC