System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-112
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Figure 4-61 FAR_EL3 bit assignments
Table 4-102 shows the FAR_EL3 bit assignments.
To access the FAR_EL3:
MRS <Xt>, FAR_EL3 ; Read EL3 Fault Address Register
MSR FAR_EL3, <Xt> ; Write EL3 Fault Address Register
4.3.68 Physical Address Register, EL1
The PAR_EL1 characteristics are:
Purpose The Physical Address returned from an address translation.
Usage constraints This register is accessible as follows:
Configurations PAR_EL1 is architecturally mapped to AArch32 register PAR(NS). See
Physical Address Register on page 4-251.
Attributes PAR_EL1 is a 64-bit register.
Figure 4-62 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address
conversion completes successfully.
Figure 4-62 PAR_EL1 pass bit assignments
Table 4-102 FAR_EL3 bit assignments
Bits Name Function
[63:0] VA The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from a misaligned PC,
taken in EL3.
If a memory fault that sets the FAR is generated from one of the data cache instructions, this field holds the address
specified in the register argument of the instruction.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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