ARM Cortex-A53 MPCore - Page 191

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-130
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations The CPUMERRSR_EL1 is:
• Architecturally mapped to the AArch64 CPUMERRSR register. See
CPU Memory Error Syndrome Register on page 4-273.
• There is one copy of this register that is used in both Secure and
Non-secure states.
• A write of any value to the register updates the register to
0 .
Attributes CPUMERRSR_EL1 is a a 64-bit register.
Figure 4-143 on page 4-276 shows the CPUMERRSR_EL1 bit assignments.
Figure 4-73 CPUMERRSR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
24 23 21 20
Other error
count
Repeat error
count
3132 063
RES
0
4748 40 39 30
Valid
RAMID
18 17
RES
0
CPUID/Way
RAM address
Fatal
RES
0
12 1162