System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-204
ID021414 Non-Confidential
To access the NSACR:
MRC p15, 0, <Rt>, c1, c1, 2 ; Read NSACR into Rt
MCR p15, 0, <Rt>, c1, c1, 2 ; Write Rt to NSACR
4.5.33 Secure Debug Control Register
The SDCR characteristics are:
Purpose Controls debug and performance monitors functionality in Secure state.
Usage constraints This register is accessible as follows:
Configurations SDCR is mapped to AArch64 register MDCR_EL3.
Attributes SDCR is a 32-bit register.
Figure 4-104 shows the SDCR bit assignments.
Figure 4-104 SDCR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
---RW-RW RW
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