System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-208
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations HSCTLR is architecturally mapped to AArch64 register SCTLR_EL2.
See System Control Register, EL2 on page 4-58.
Attributes HSCTLR is a 32-bit register.
Figure 4-106 shows the HSCTLR bit assignments.
Figure 4-106 HSCTLR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
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