System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-211
ID021414 Non-Confidential
To access the HSCTLR:
MRC p15,4,<Rt>,c1,c0,0 ; Read HSCTLR into Rt
MCR p15,4,<Rt>,c1,c0,0 ; Write Rt to HSCTLR
4.5.36 Hyp Configuration Register
The HCR characteristics are:
Purpose Provides configuration controls for virtualization, including defining
whether various Non-secure operations are trapped to Hyp mode.
Usage constraints This register is accessible as follows:
Configurations HCR is architecturally mapped to AArch64 register HCR_EL2[31:0]. See
Hypervisor Configuration Register on page 4-60.
Attributes HCR is a 32-bit register.
Figure 4-107 shows the HCR bit assignments.
Figure 4-107 HCR bit assignments
[0] M MMU enable. This is a global enable bit for the EL2 stage 1 MMU:
0
EL2 stage 1 MMU disabled.
1
EL2 stage 1 MMU enabled.
If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is
UNKNOWN.
Table 4-201 HSCTLR bit assignments (continued)
Bits Name Function
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW -
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