System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-218
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations • HDCR is architecturally mapped to AArch64 register MDCR_EL2.
See Hyp Debug Control Register on page 4-66.
• This register is accessible only at EL2 or EL3.
Attributes HDCR is a 32-bit register.
Figure 4-109 shows the HDCR bit assignments.
Figure 4-109 HDCR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
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