ARM Cortex-A53 MPCore - Page 309

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-248
ID021414 Non-Confidential
DFAR (S) is architecturally mapped to AArch64 register FAR_EL2[31:0].
See Fault Address Register, EL2 on page 4-104.
Attributes DFAR is a 32-bit register.
Figure 4-126 shows the DFAR bit assignments.
Figure 4-126 DFAR bit assignments
on page 4-104Table 4-224 shows the DFAR bit assignments.
To access the DFAR:
MRC p15, 0, <Rt>, c6, c0, 0 ; Read DFAR into Rt
MCR p15, 0, <Rt>, c6, c0, 0 ; Write Rt to DFAR
4.5.56 Instruction Fault Address Register
The IFAR characteristics are:
Purpose Holds the virtual address of the faulting address that caused a synchronous
Prefetch Abort exception.
Usage constraints This register is accessible as follows:
Configurations IFAR (NS) is architecturally mapped to AArch64 register
FAR_EL1[63:32]. See Fault Address Register, EL1 on page 4-103.
IFAR (S) is architecturally mapped to AArch32 register HIFAR.
IFAR (S) is architecturally mapped to AArch64 register FAR_EL2[63:32].
See Fault Address Register, EL2 on page 4-104.
Attributes IFAR is a 32-bit register.
Figure 4-127 shows the IFAR bit assignments.
Figure 4-127 IFAR bit assignments
31
0
VA of faulting address of synchronous Data Abort exception
Table 4-224 DFAR bit assignments
Bits Name Function
[31:0] VA The Virtual Address of faulting address of synchronous Data Abort exception
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
IFAR(S) - - - RW - - RW
IFAR(NS) - - RW - RW RW -
31
0
VA of faulting address of synchronous Prefetch Abort exception