System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-272
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
The CPUECTLR can be written dynamically.
Configurations The CPUECTLR is:
• Architecturally mapped to the AArch64 CPUECTLR_EL1 register.
See CPU Extended Control Register, EL1 on page 4-128.
Attributes CPUECTLR is a 64-bit register.
Figure 4-141 shows the CPUECTLR bit assignments.
Figure 4-141 CPUECTLR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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