Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-5
ID021414 Non-Confidential
When in L2 read allocate mode, loads behave as normal and can still cause
linefills, and writes still lookup in the cache but, if they miss, they write
out to L3 rather than starting a linefill. L2 read allocate mode continues
until there is a cacheable write burst that is not a full cache line, or there is
a load to the same line as is currently being written to L3.
In AArch64, CPUACTLR_EL1.L1RADIS configures the L1 read allocate
mode threshold, and CPUACTLR_EL2.RADIS configures the L2 read
allocate mode threshold. See CPU Auxiliary Control Register, EL1 on
page 4-124.
In AArch32, CPUACTLR.L1RADIS configures the L1 read allocate
mode threshold, and CPUACTLR.RADIS configures the L2 read allocate
mode threshold. See CPU Auxiliary Control Register on page 4-269.
Data cache invalidate on reset
The ARMv8-A architecture does not support an operation to invalidate the
entire data cache. If this function is required in software, it must be
constructed by iterating over the cache geometry and executing a series of
individual invalidate by set/way instructions.
The Cortex-A53 processor automatically invalidates caches on reset
unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE
pins. It is therefore not necessary for software to invalidate the caches on
startup.
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