Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-15
ID021414 Non-Confidential
The CP15 Data Cache Data Read Operation returns two entries from the cache in Data Register
0 and Data Register 1 corresponding to the 16-bit aligned offset in the cache line:
Data Register 0 Bits[31:0] data from cache offset+
0b000
.
Data Register 1 Bits[31:0] data from cache offset+
0b100
.
The 64 bits of cache data is returned in Data register 0 and Data register 1.
Table Table 6-8 describes the MOESI state.
6.7.2 Instruction cache tag and data encoding
The Cortex-A53 processor instruction cache is significantly different from the data cache and
this is shown in the encodings and data format used in the CP15 operations used to access the
tag and data memories. Table 6-9 shows the encoding required to select a given cache line. The
set-index range parameter (S) is determined by:
S = log
2
(Instruction cache size (Byte) / 2*32)) for the 2-way set-associative cache.
Data Register 0 [3] Outer Allocation Hint.
Data Register 0 [2] Outer Shareability, from Dirty RAM.
Data Register 0 [1:0]
Partial MOESI state, from Dirty RAM. See Table 6-8.
Table 6-8 MOESI state
Tag RAM
partial MOESI bits
Dirty RAM
partial MOESI bits
MOESI state
00 xx Invalid (I)
01 x0 SharedClean (S)
x1 SharedDirty (O)
1x x0 UniqueClean (E)
x1 UniqueDirty (M)
Table 6-7 Data cache tag data format (continued)
Register Bit-field Description
Table 6-9 Instruction cache tag and data location encoding
Bit-field of Rd Description
[31] Cache Way
[30:S+5] Unused
[S+4:6] Set index
[5:2] Line offset
[1:0] Unused
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