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Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-13
ID021414 Non-Confidential
To access the DBGWCRn in AArch32 Execution state, read or write the CP14 register with:
MRC p14, 0, <Rt>, c0, cn, 7; Read Debug Watchpoint Control Register n
MCR p14, 0, <Rt>, c0, cn, 7; Write Debug Watchpoint Control Register n
To access the DBGWCRn_EL1 in AArch64 Execution state, read or write the register with:
MRS <Xt>, DBGWCRn_EL1; Read Debug Watchpoint Control Register n
MSR DBGWCRn_EL1, <Xt>; Write Debug Watchpoint Control Register n
The DBGWCRn_EL1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x8n8
. The range of n for DBGWCRn_EL1 is 0 to 3.
11.4.3 Debug Claim Tag Set register
The DBGCLAIMSET_EL1characteristics are:
Purpose Used by software to set CLAIM bits to 1.
Usage constraints This register is accessible as follows:
[4:3] LSC Load/store access control. This field enables watchpoint matching for the type of access. The possible values are:
0b00
Reserved.
0b01
Match on any load, Load-Exclusive, or swap.
0b10
Match on any store, Store-Exclusive or swap.
0b11
Match on all type of access.
[2:1] PAC Privileged Access Control. This field enables watchpoint matching conditional on the mode of the processor. This
field is used with the SSC and PAC fields.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for possible values of
the fields, and the access modes and security states that can be tested.
Note
For all cases the match refers to the privilege level of the access, not the mode of the processor. For
example, if the watchpoint is configured to match only accesses at PL1 or higher, and the processor
executes an
LDRT
instruction in a PL1 mode, the watchpoint does not match.
Permitted values of this field are not identical to those for the DBGBCR. In the DBGBCR the value
b00
permitted.
[0] E Watchpoint Enable. This bit enables the watchpoint:
0
Watchpoint disabled.
1
Watchpoint enabled.
A watchpoint never generates a Watchpoint debug event when it is disabled.
Note
The value of DBGWCR.E is UNKNOWN on reset. A debugger must ensure that DBGWCR.E has a defined value
before it programs DBGDSCR[15:14] to enable debug.
Table 11-5 DBGWCRn_EL1 bit assignments (continued)
Bits Name Function
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RWRWRW RW

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