Functional Description
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 2-21
ID021414 Non-Confidential
Entry into L2 WFI low-power state can occur only if specific requirements are met and the
following sequence applied:
• All cores are in WFI low-power state and therefore, the STANDBYWFI output for each
core is asserted. Assertion of all the cores STANDBYWFI outputs guarantee that all the
cores are in idle and low power state. All clocks in the cores, with the exception of a small
amount of clock wake up logic, are disabled.
• If configured with ACE, the SoC asserts the input pin ACINACTM to idle the AXI
master interface. This indicates that no snoop requests will be made from the external
memory system.
• If configured with a CHI interface, the SoC asserts the input pin SINACT to idle the CHI
master interface. This indicates that no snoop requests will be made from the external
memory system.
• If configured with an ACP interface, the SoC asserts the AINACTS input pin to idle the
ACP interface. This indicates that the SoC sends no more transaction on the ACP
interface.
When the L2 memory system completes the outstanding transactions for AXI or CHI interfaces,
it can then enter the low power state, L2 WFI low-power state. On entry into L2 WFI low-power
state, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2 guarantees that the L2
memory system is idle and does not accept new transactions.
Exit from L2 WFI low-power state occurs on one of the following events:
• A physical IRQ or FIQ interrupt.
• A debug event.
• Powerup or warm reset.
When a core exits from WFI low-power state, STANDBYWFI for that core is deasserted. When
the L2 memory system logic exits from WFI low-power state, STANDBYWFIL2 is deasserted.
The SoC must continue to assert ACINACTM or SINACT until STANDBYWFIL2 has
deasserted.
Figure 2-10 shows the L2 WFI timing for a 4-core configuration.
Figure 2-10 L2 Wait For Interrupt timing
Individual core shutdown mode
In this mode, the PDCPU power domain for an individual core is shut down and all state is lost.
For full shutdown of the Cortex-A53 processor, including implementations with a single core,
see Cluster shutdown mode without system driven L2 flush on page 2-22 and Cluster shutdown
mode with system driven L2 flush on page 2-23.
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