ARM Cortex-A53 MPCore - Page 445

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-43
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Table 11-29 shows the bit assignments for a ROMENTRY register.
The Physical Address of a debug component is determined by shifting the address offset 12
places to the left and adding the result to the Physical Address of the Cortex-A53 processor
ROM Table.
Table 11-30 shows the offset values for all ROMENTRY values when a v8 memory map is
implemented. Table 11-31 on page 11-44 shows the offset values for all ROMENTRY values
when a legacy v7 memory map is implemented.
If a core is not implemented, the ROMENTRY registers for its debug, CTI, PMU and ETM trace
unit components are
0x00000000 when a v8 memory map is implemented and 0x00000002 when
a v7 memory map is implemented.
Table 11-29 ROMENTRY bit assignments
Bits Name Function
[31:12] Address offset Address offset for the debug component.
Note
Negative values of address offsets are permitted using the two’s complement of the offset.
[11:2] - Reserved, RES0.
[1] Format Format of the ROM table entry. The value for all ROMENTRY registers is:
0 End marker.
1 32-bit format.
[0]
Component present
a
Indicates whether the component is present:
0 Component is not present.
1 Component is present.
a. The components for core 0 are always present. The entries for core 1, 2, and 3 components depend on your configuration.
Table 11-30 v8 ROMENTRY values
Name Debug component Offset value ROMENTRY value
ROMENTRY0 Core 0 Debug
0x00010 0x00010003
ROMENTRY1 Core 0 CTI 0x00020 0x00020003
ROMENTRY2 Core 0 PMU 0x00030 0x00030003
ROMENTRY3 Core 0 ETM trace unit 0x00040 0x00040003
ROMENTRY4 Core 1 Debug 0x00110
0x00110003
a
ROMENTRY5 Core 1 CTI 0x00120
0x00120003
a
ROMENTRY6 Core 1 PMU 0x00130
0x00130003
a
ROMENTRY7 Core 1 ETM trace unit 0x00140
0x00140003
a
ROMENTRY8 Core 2 Debug 0x00210
0x00210003
a
ROMENTRY9 Core 2 CTI 0x00220
0x00220003
a
ROMENTRY10 Core 2 PMU 0x00230
0x00230003
a
ROMENTRY11 Core 2 ETM trace unit 0x00240
0x00240003
a