Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-4
ID021414 Non-Confidential
12.2.5 External register access permissions
External access permission to the PMU registers is subject to the conditions at the time of the
access. Table 12-1 describes the processor response to accesses through the external debug and
memory-mapped interfaces.
Table 12-2 shows an example of external register condition codes for access to a performance
monitor register. To determine the access permission for the register, scan the columns from left
to right. Stop at the first column whose condition is true, the entry gives the register access
permission and scanning stops.
Table 12-1 External register conditions
Name Condition Description
Off EDPRSR.PU is 0 Processor power domain is completely off, or in a low-power state where the
processor power domain registers cannot be accessed.
DLK EDPRSR.DLK is 1 OS Double Lock is locked.
OSLK OSLSR_EL1.OSLK is 1 OS Lock is locked.
EPMAD
AllowExternalPMUAccess() == FALSE
External performance monitors access is disabled. When an error is returned
because of an EPMAD condition code, and this is the highest priority error
condition, EDPRSR.SPMAD is set to 1. Otherwise SPMAD is unchanged.
SLK Memory-mapped interface only Software lock is locked. For the external debug interface, ignore this column.
Default - None of the conditions apply, normal access.
Table 12-2 External register condition code example
Off DLK OSLK EPMAD SLK Default
-- - - RO/WIRO
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