ARM Cortex-A53 MPCore

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Functional Description

ID021414 Non-Confidential

2. Follow steps 1 to 2 in Individual core shutdown mode on page 2-21.

3. If the ACP interface is configured, ensure that any master connected to the interface does

not send new transactions, then assert AINACTS.

4. Clean and invalidate all data from the L2 Data cache.

5. Follow steps 3 to 9 in Individual core shutdown mode on page 2-21.

6. In an ACE configuration, assert ACINACTM or, in a CHI configuration, assert

SINACT. Then wait until the STANDBYWFIL2 output is asserted to indicate that the

L2 memory system is idle. All Cortex-A53 processor implementations contain an L2

memory system, including implementations without an L2 cache.

7. Activate the cluster output clamps.

8. Remove power from the PDCORTEXA53 and PDL2 power domains.

Note

For device powerdown, all operations on the lead core must occur after the equivalent step on

all non-lead cores.

To power up the cluster, apply the following sequence:

1. For each core in the cluster, assert nCPUPORESET LOW.

2. Assert nL2RESET LOW and hold L2RSTDISABLE LOW.

3. Apply power to the PDCORTEXA53 and PDL2 domains while keeping the signals

described in steps 1. and 2. LOW.

4. Release the cluster output clamps.

5. Continue a normal cold reset sequence.

Cluster shutdown mode with system driven L2 flush

This is the mode where the PDCORTEXA53, PDL2, and PDCPU power domains are shut down

and all state is lost. To power down the cluster, apply the following sequence:

1. Ensure all cores are in shutdown mode, see Individual core shutdown mode on page 2-21.

2. The SoC asserts the AINACTS signal to idle the ACP. This is necessary to prevent ACP

transactions from allocating new entries in the L2 cache while the hardware cache flush

is occurring.

3. Assert L2FLUSHREQ HIGH.

4. Hold L2FLUSHREQ HIGH until L2FLUSHDONE is asserted.