Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-17
ID021414 Non-Confidential
Figure 13-7 TRCAUXCTLR bit assignments
Table 13-8 shows the TRCAUXCTLR bit assignments.
Table 13-8 TRCAUXCTLR bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7] COREIFEN Keep core interface enabled regardless of trace enable register state. The possible values are:
0
Core interface enabled is set by trace enable register state.
1
Enable core interface, regardless of trace enable register state.
[6] - Reserved,
RES0.
[5] AUTHNOFLUSH Do not flush trace on de-assertion of authentication inputs. The possible values are:
0
ETM trace unit FIFO is flushed and ETM trace unit enters idle state when
DBGEN or NIDEN is LOW.
1
ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state
when DBGEN or NIDEN is LOW.
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.
[4] TSNODELAY Do not delay timestamp insertion based on FIFO depth. The possible values are:
0
Timestamp packets are inserted into FIFO only when trace activity is LOW.
1
Timestamp packets are inserted into FIFO irrespective of trace activity.
[3] SYNCDELAY Delay periodic synchronization if FIFO is more than half-full. The possible values are:
0
SYNC packets are inserted into FIFO only when trace activity is low.
1
SYNC packets are inserted into FIFO irrespective of trace activity.
To Next Page
Loading...
