Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-39
ID021414 Non-Confidential
Figure 13-33 TRCIDR0 bit assignments
Table 13-34 shows the TRCIDR0 bit assignments.
Table 13-34 TRCIDR0 bit assignments
Bits Name Function
[31:30] - Reserved,
RES0.
[29] COMMOPT Indicates the meaning of the commit field in some packets:
1
Commit mode 1.
[28:24] TSSIZE Global timestamp size field:
0b01000
Implementation supports a maximum global timestamp of 64 bits.
[23:17] - Reserved,
RES0.
[16:15] QSUPP Indicates Q element support:
b00
Q elements not supported.
[14] QFILT Indicates Q element filtering support:
b0
Q element filtering not supported.
[13:12] CONDTYPE Indicates how conditional results are traced:
b00
Conditional trace not supported.
[11:10] NUMEVENT Number of events supported in the trace, minus 1:
b11
Four events supported.
[9] RETSTACK Return stack support:
1
Return stack implemented.
[8] - Reserved,
RES0.
[7] TRCCCI Support for cycle counting in the instruction trace:
1
Cycle counting in the instruction trace is implemented.
[6] TRCCOND Support for conditional instruction tracing:
0
Conditional instruction tracing is not supported.
[5] TRCBB Support for branch broadcast tracing:
1
Branch broadcast tracing is implemented.
[4:3] TRCDATA Conditional tracing field:
0b00
Tracing of data addresses and data values is not implemented.
[2:1] INSTP0 P0 tracing support field:
0b00
Tracing of load and store instructions as P0 elements is not supported.
[0] - Reserved,
RES1.
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