ARM Cortex-A53 MPCore - Page 536

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-41
ID021414 Non-Confidential
• Context ID.
• Instruction address.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-35 shows the TRCIDR2 bit assignments.
Figure 13-35 TRCIDR2 bit assignments
Table 13-36 shows the TRCIDR2 bit assignments.
The TRCIDR2 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0x1E8 .
13.8.34 ID Register 3
The TRCIDR3 characteristics are:
Purpose Indicates:
• Whether TRCVICTLR is supported.
• The number of cores available for tracing.
• If an exception level supports instruction tracing.
• The minimum threshold value for instruction trace cycle counting.
• Whether the synchronization period is fixed.
31 025 24 1415 10 9 5 4
IASIZE
29 28 20 19
CIDSIZEVMIDSIZEDASIZEDVSIZECCSIZERES0
Table 13-36 TRCIDR2 bit assignments
Bits Name Function
[31:29] - Reserved,
RES0.
[28:25] CCSIZE Size of the cycle counter in bits minus 12:
0x0 The cycle counter is 12 bits in length.
[24:20] DVSIZE Data value size in bytes:
0x00 Data value tracing is not implemented.
[19:15] DASIZE Data address size in bytes:
0x00 Data address tracing is not implemented.
[14:10] VMIDSIZE Virtual Machine ID size:
0x1 Virtual Machine ID is 8 bits.
[9:5] CIDSIZE Context ID size in bytes:
0x4 Maximum of 32-bit Context ID size.
[4:0] IASIZE Instruction address size in bytes:
0x8 Maximum of 64-bit address size.