Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-44
ID021414 Non-Confidential
The TRCIDR4 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0x1F0
.
13.8.36 ID Register 5
The TRCIDR5 characteristics are:
Purpose Returns how many resources the trace unit supports.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-38 shows the TRCIDR5 bit assignments.
Figure 13-38 TRCIDR5 bit assignments
Table 13-39 shows the TRCIDR5 bit assignments.
[8] SUPPDAC Indicates whether the implementation supports data address comparisons: This value is:
0
Data address comparisons are not implemented.
[7:4] NUMDVC Indicates the number of data value comparators available for tracing:
0x0
Data value comparators not implemented.
[3:0] NUMACPPAIRS Indicates the number of address comparator pairs available for tracing:
0x4
Four address comparator pairs are implemented.
Table 13-38 TRCIDR4 bit assignments (continued)
Bits Name Function
Table 13-39 TRCIDR5 bit assignments
Bits Name Function
[31] REDFUNCNTR Reduced Function Counter implemented:
0
Reduced Function Counter not implemented.
[30:28] NUMCCNTR Number of counters implemented:
b010
Two counters implemented.
[27:25] NUMSEQSTATE Number of sequencer states implemented:
b100
Four sequencer states implemented.
[24] - Reserved,
RES0.
To Next Page
Loading...
