Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-62
ID021414 Non-Confidential
13.8.56 Device Affinity Register 0
The TRCDEVAFF0 characteristics are:
Purpose Provides an additional core identification mechanism for scheduling
purposes in a cluster.
TRCDEVAFF0 is a read-only copy of MPIDR accessible from the
external debug interface.
Usage constraints This register is accessible as follows:
Configurations The TRCDEVAFF0 is:
• Architecturally mapped to the AArch64 MPIDR_EL1[31:0]
register. See Multiprocessor Affinity Register on page 4-15.
• Architecturally mapped to external TRCDEVAFF0 register.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes TRCDEVAFF0 is a 32-bit register.
Figure 13-58 shows the TRCDEVAFF0 bit assignments.
Figure 13-58 TRCDEVAFF0 bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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