Programmers Model
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 3-8
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Taking an exception selects the default stack pointer for the target exception level,
meaning SP maps to the SP_ELx stack pointer register, where x is the exception
level.
Software executing in the target exception level can execute an
MSR SPSel, #Imm1
instruction to select whether to use the default SP_ELx stack pointer, or the
SP_EL0 stack pointer.
The selected stack pointer can be indicated by a suffix to the exception level:
t Indicates use of the SP_EL0 stack pointer.
h Indicates use of the SP_ELx stack pointer.
Table 3-2 shows the set of AArch64 stack pointer options.
AArch32 In AArch32 state, each mode that can be the target of an exception has its own
banked copy of the stack pointer. For example, the banked stack pointer for Hyp
mode is called SP_hyp. Software executing in one of these modes uses the banked
stack pointer for that mode.
The modes that have banked copies of the stack pointer are FIQ mode, IRQ mode,
Supervisor mode, Abort mode, Undefined mode, Hyp mode, and Monitor mode.
Software executing in User mode or System mode uses the User mode stack
pointer, SP_usr.
For more information, see AArch32 execution modes on page 3-10.
3.2.6 ARMv8 security model
The Cortex-A53 processor implements all of the exception levels. This means:
• EL3 exists only in Secure state and a change from Secure state to Non-secure state is made
only by an exception return from EL3.
• EL2 exists only in Non-secure state.
To provide compatibility with ARMv7, the exception levels available in Secure state are
modified when EL3 is using AArch32. The following sections describe the security model:
• Security model when EL3 is using AArch64.
• Security model when EL3 is using AArch32 on page 3-9.
Security model when EL3 is using AArch64
When EL3 is using AArch64, Figure 3-1 on page 3-9 shows the security model, and the
expected use of the different exception levels. This figure shows how instances of EL0 and EL1
are present in both security states.
Table 3-2 AArch64 stack pointer options
Exception level AArch64 stack pointer options
EL0 EL0t
EL1 EL1t, EL1h
EL2 EL2t, EL2h
EL3 EL3t, EL3h
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