Signal Descriptions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. A-27
ID021414 Non-Confidential
DBGPWRDUP[CN:0] Input Processor powered up.
DBGPWRUPREQ[CN:0] Output Power up request:
0
Power down debug request to the power controller.
1
Power up request to the power controller.
DBGL1RSTDISABLE Input Disable L1 data cache automatic invalidate on reset functionality:
0
Enable automatic invalidation of L1 data cache on reset.
1
Disable automatic invalidation of L1 data cache on reset.
This pin is sampled only during reset of the processor.
Table A-35 Miscellaneous Debug signals (continued)
Signal Direction Description
To Next Page
Loading...
