Revisions
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. C-4
ID021414 Non-Confidential
Table C-4 Differences between Issue C and Issue D
Change Location Affects
Updated descriptions of Memory Attribute
Indirection Registers
Memory Attribute Indirection Register, EL1 on page 4-116
Memory Attribute Indirection Register, EL2 on page 4-118
Memory Attribute Indirection Register, EL3 on page 4-118
Memory Attribute Indirection Registers 0 and 1 on page 4-259
All revisions
Instruction mnemonic updated 64-bit registers on page 4-147 All revisions
Added note to CPUECTLR.SMPEN bit description Table 4-245 on page 4-273 All revisions
SELx signal reduced from 6 bits to 5 bits Figure 13-21 on page 13-30
Table 13-22 on page 13-30
All revisions
Updated number of external inputs to trace unit Table 13-39 on page 13-44 All revisions
Footnote added to SAMMNBASE[39,24]
description
Table A-17 on page A-15 All revisions
To Previous Page
Loading...
