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Panasonic MN103S

Panasonic MN103S
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Chapter 5
Interrupt Controller
V - 12 Control Registers
5.2.4 Non-Maskable Interrupt Control Register
If a NMI interrupt request is issued, The flag corresponding to the request is set. After the NMI interrupt request is
accepted, the flag is cleared by software in the NMI interrupt processing program. When the flag is set to “1”, the
flag can be cleared by writing “1”. Table: 5.2.5 shows the relationship between the flag status, the data written to
the flag, and the flag status after the data is written.
Table:5.2.5 Changes of Interrupt Request Flags
Non-maskable Interrupt Control Register (NMICR: 0x00008900) [8, 16-bit access register]
..
NMI cannot be generated by software.
..
Flag status before write Write data Flag status after write Flag change
0 0 0 No change
0 1 0 No change
1 0 1 No change
1 1 0 Flag cleared
bp 1514131211109876543 2 1 0
Flag -------------
SYSEF
WDIF -
At reset 0000000000000 0 0 0
Access RRRRRRRRRRRRRR/WR/WR
bp Flag Description Set condition
15-3 - - -
2 SYSEF
System error interrupt request flag 0: No interrupt request
1: Interrupt request
1WDIF
Watchdog timer overflow interrupt
request flag
0: No interrupt request
1: Interrupt request
0-- -

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